The present invention relates to a semiconductor device and a method for fabricating the device, and more particularly relates to a semiconductor device in which MOS transistors are formed on an SOI (silicon on insulator) substrate, and a method for fabricating the device.
Conventionally, semiconductor devices that have a MOS structure, in which a Pch-transistor and an Nch-transistor are formed on an SOI substrate, have found a wide variety of applications. Particularly, the patent document 1 (Japanese Laid-Open Patent Publication No. 3111947 (FIG. 1 and descriptions thereof)) discloses a semiconductor device for use in a driving circuit in a plasma display, which semiconductor device employs MOS transistors with an offset structure in order to obtain a high breakdown-voltage characteristic.
FIG. 6 is a cross-sectional view of a conventional semiconductor device that includes transistors with an offset structure as the semiconductor device disclosed in the patent document 1 does. In the semiconductor device shown in FIG. 6, an N-channel transistor and a P-channel transistor, each being a MOS transistor with an offset structure, are formed on a common SOI substrate.
As shown in FIG. 6, the conventional semiconductor device includes a buried oxide film 102, a semiconductor layer 103, trench isolation regions 104, field oxide films 105a through 105d, and an interlevel dielectric film 106. The buried oxide film 102 is formed on a supporting substrate (silicon substrate) 101. The semiconductor layer 103 is formed on the buried oxide film 102. The trench isolation regions 104 are provided to divide the semiconductor layer 103 into a plurality of active regions 103a, 103b, . . . The field oxide films 105a through 105d are formed by a LOCOS technique. The interlevel dielectric film 106 covers the semiconductor layer 103.
The SOI substrate in the conventional semiconductor device is formed by polishing one of the two silicon substrates, each containing a low concentration of a P-type impurity, that are connected with each other via the buried oxide film 102 until the polished substrate becomes thin.
An N-channel transistor is formed in the first active region 103a. The N-channel transistor includes a back-gate contact region 111, a source electrode 112, a source region 113, a gate electrode 114a, an extraction gate electrode 114b, a drain electrode 115, a body region 116, a gate oxide film 118, a drain offset region 119, and a drain contact region 120. The back-gate contact region 111 contains a P-type impurity at a high concentration. The source electrode 112 is made of metal. The source region 113 contains an N-type impurity at a high concentration. The gate electrode 114a is made of polysilicon, and the extraction gate electrode 114b is made of metal. The drain electrode 115 is made of metal. The body region 116 contains a P-type impurity at a low concentration. The gate oxide film 118 is made of a thin silicon oxide film. The drain offset region 119 contains an N-type impurity at a low concentration. The drain contact region 120 contains an N-type impurity at a high concentration. In the N-channel transistor, the gate electrode 114a extends not only over the gate oxide film 118 but also over the field oxide film 105a. In other words, a part of the field oxide film 105a functions as a gate insulating film.
The N-channel transistor is formed in the first active region 103a, which is formed by surrounding with the trench isolation regions 104 a given region in the low-concentration-P-type-impurity-containing semiconductor layer 103 formed on the buried oxide film 102 on the supporting substrate 101, so that the first active region 103a is isolated from the peripheral devices by the insulators.
The body region 116 is formed shallowly by implanting ions of a P-type impurity (boron, for example) to a medium concentration into a surface region of the first active region 103a. The body region 116 has an impurity concentration profile in which the concentration shows a maximum value near the surface and decreases with distance from the surface. The high-concentration-N-type-impurity-containing source region 113, which is formed in a surface region within the body region 116, is electrically connected with the body region 116. In order to make the electrical connection be in good condition, the high-concentration-P-type-impurity-containing back-gate contact region 111 is provided, and the source region 113 is electrically connected to the body region 116 via the source electrode 112.
The drain offset region 119 is an N-well, which is formed by implanting ions of phosphorous as an N-type impurity into the first active region 103a. The drain offset region 119 has an impurity concentration profile in which the concentration shows a maximum value near the surface and decreases with distance from the surface. The drain offset region 119 is formed slightly spaced apart from the body region 116 within the first active region 103a. The drain contact region 120 is formed by implanting ions of an N-type impurity (arsenic) to a high concentration into a surface region within the drain offset region 119. The drain contact region 120 is in contact with the drain electrode 115.
The field oxide film 105a is formed on the first active region 103a between the source region 113 and the drain contact region 120, so as to be located closer to the drain contact region 120. The gate oxide film 118 is formed on the first active region 103a between the source region 113 and the drain contact region 120, so as to be located closer to the source region 113. The gate electrode 114a is formed extending over the gate oxide film 118 as well as over a part of the field oxide film 105a. The gate electrode 114a is formed to be connected to an end portion of the field oxide film 105a, and also serves as a kind of field plate, so that electric field concentration will not be apt to occur in the vicinity of the source region 113.
Further, a P-channel transistor is formed in the second active region 103b. The P-channel transistor includes a back-gate contact region 121, a source electrode 122, a source region 123, a gate electrode 124a, an extraction gate electrode 124b, a drain electrode 125, a body region 126, a field oxide film 105d, a drain offset region 129, and a drain contact region 130. The back-gate contact region 121 contains an N-type impurity at a high concentration. The source electrode 122 is made of metal. The source region 123 contains a P-type impurity at a high concentration. The gate electrode 124a is made of polysilicon, and the extraction gate electrode 124b is made of metal. The drain electrode 125 is made of metal. The body region 126 contains an N-type impurity at a low concentration. The field oxide film 105d acts as a gate insulating film. The drain offset region 129 contains a P-type impurity at a low concentration. The drain contact region 130 contains a P-type impurity at a high concentration. In the P-channel transistor, a gate oxide film of a thin silicon oxide such as shown in the N-channel transistor is not formed, and the entire gate electrode 124a is provided on the field oxide film 105d. 
The P-channel transistor is formed in the second active region 103b, which is formed by surrounding with the trench isolation regions 104 a given region in the low-concentration-P-type-impurity-containing semiconductor layer 103 formed on the buried oxide film 102 on the supporting substrate 101 so that the second active region 103b is isolated from the peripheral devices by the insulators.
The drain offset region 129 is a P-well, which is formed by implanting ions of boron as a P-type impurity into the second active region 103b. The drain offset region 129 has an impurity concentration profile in which the concentration shows a maximum value near the surface and decreases with distance from the surface. The drain contact region 130 is formed by implanting ions of a P-type impurity (boron) to a high concentration into a surface region within the drain offset region 129. The drain contact region 130 is in contact with the drain electrode 125.